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Power Integrations

Failure Analysis Intern

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Recruitment began on May 15, 2026
and the job listing Expires on June 15, 2026
Internships
Apply Now

Role Description:

  • Assist FA engineers in performing failure analysis on customer’s RMA returns and internal engineering requests
  • Learn and perform hands-on in electrical fault isolation and defect characterization at both IC (or silicon level) and power supply
    • Inspect and document incoming RMA returns both at IC’s and Power Supply levels
    • Support electrical debugging activities, including performing impedance measurements, ATE test, and curve tracing of IC’s
  • Work with senior engineers to analyze test data and perform physical analysis (e.g., optical microscopy and CSAM/SEM imaging)
  • Support FA engineers in data collection, documentation and contribution to technical reports

Expected Learning Outcomes:

  • Gain hands-on experience in semiconductor failure analysis workflows
  • Develop understanding of electrical fault isolation and physical analysis techniques
  • Learn to interpret I-V curve and ATE test datalogs
  • Build practical knowledge of FA tools such as XRAY, CSAM, probing systems, SEM/FIB
  • Learn technical reporting and communication skills
  • Develop collaboration experience in engineering environments

Deliverables:

  • Document failure analysis findings with observations and preliminary conclusions
  • Data summaries and failure trend insights
  • Contributions to root cause analysis under engineer supervision
  • Presentations summarizing internship work or failure case studies

Qualifications & Requirements

Required Skills:

  • Fundamental knowledge of analog and digital circuits
  • Basic understanding of semiconductor device physics and IC fabrication processes
  • Exposure to lab tools such as curve tracer, Oscilloscopes, Source meters, and DMM
  • Basic technical report writing and documentation skills

Preferred Skills:

  • Completed academic projects that required using S/W tools such as Cadence/Synopsis, MATLAB, Spice etc.. to design, simulate, assemble, and test the design at final products
  • Hands-on lab or academic project experiences in device/PCB level characterization
  • Familiarity with IC/PCB-level schematics and layout
  • Understanding of analog, mixed-signal, or power IC operation
  • Exposure to some failure analysis techniques such as optical micro-scopes, XRAY, and SEM

Education Level: 3rd year Bachelors or Masters Degree

Field(s) of Study: Electrical/Electronics Engineering, Power Electronics Engineering

Power Integrations is committed to building teams that drive innovation and therefore review a range of factors when determining compensation. The hourly pay range for this internship is $32 to $40. Our pay ranges are determined by role, level, qualifications and work location.

The range displayed on the job posting reflects the minimum and maximum target for this intern in California. Within the range, individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training.

Apply Now

Contact & Location

Phone
909-869-2342
Email
career@cpp.edu
Address

Career Center Building 97 - Room 128
3801 West Temple Avenue
Pomona, CA 91786

Career Service Hours

Day of the week
Regular Hours Drop-in Advising
M Monday 8:00 am - 5:00 pm 10:00 am - 3:00 pm
T Tuesday 8:00 am - 5:00 pm 10:00 am - 3:00 pm
W Wednesday 8:00 am - 5:00 pm 10:00 am - 3:00 pm
TH Thursday 8:00 am - 5:00 pm 10:00 am - 3:00 pm
F Friday 8:00 am - 5:00 pm 10:00 am - 3:00 pm

Current students can schedule an appointment with a Career Coach through CPP Connect.

Alumni do NOT have access to CPP Connect and must register with the Career Center for Appointment Access.

Phone
909-869-2342
Email
career@cpp.edu
Address

Career Center Building 97 - Room 128
3801 West Temple Avenue
Pomona, CA 91786

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